The basic architecture of most data processing systems today includes a digital processor and random access memory. For economic reasons, the random access memory ("RAM") is often dynamic random access memory ("DRAM").
DRAMs typically include an array of memory cells, with each memory cell including a capacitor for storing charge representing data. Because of charge leakage from these capacitors, data will be lost if the capacitors are not periodically refreshed. The refresh period can be no longer than the time it takes for enough charge to leak from a capacitor to change the state that is read from the capacitor (the pause time).
Recently, synchronous dynamic random access memories ("SDRAM") have been proposed to better take advantage of inherent DRAM bandwidth. With synchronous DRAMs, data is clocked in and out of the memory device at relatively high rates. For example, some synchronous DRAMs may be capable of running at speeds of 100 Mhz or more. Under certain standardization agreements, synchronous DRAMs are required to include self-refresh operations. With self-refresh operations, refresh operations are performed under control of the device itself, rather than externally. Self-refresh functions are desirable for asynchronous DRAMs as well.
Self-refresh operations are desirable, for example, where power saving is important. For example, in laptop computers, external circuitry (circuitry outside of the memory device) is often deactivated at certain times to conserve energy. With the external circuitry deactivated, it is unable to generate refresh commands for refreshing DRAMs. Thus, the self-refresh operation is necessary.
A refresh operation for a memory array usually involves sequentially selecting each row of the memory array and refreshing all of the cells of a particular row at once.
To ensure the functionality of the self-refresh operation, the self-refresh operation is typically tested in the production environment. Because DRAMs are typically high-volume parts, testing of each chip is expensive and time consuming, and saving time in the testing of each chip results in significant time savings overall. Unfortunately, existing techniques for testing the self-refresh operation are inefficient.
One technique for testing the self-refresh operation is to write data into the memory array, and then enter the self-refresh mode. After a period of time longer than the pause time, data is read out of the memory array. If the data corresponds with that which was previously written into the array, then the self-refresh operation was performed properly. A second technique involves writing background data to the memory array, and then entering the self-refresh mode that also performs writing of opposite data to the memory array. After a period of time longer than the pause time of the memory cells, the data is read out. If any of the background data still persists, then the self-refresh operation was not performed properly, as not all data was changed.
Such techniques are time consuming, since writing-in and reading-out data to the whole array are time consuming operations. These problems exist for any DRAM part that includes the self-refresh operation, and in particular to synchronous DRAMs, wherein the self-refresh operation is required.